With the increasing down-scaling of integrated circuits and increasingly demanding requirements to the speed of integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFET) were thus developed. FIG. 1 illustrate a cross-sectional view of a conventional FinFET, wherein the cross-sectional view is made crossing the fins rather than the source and drain regions. Fins 100 are formed as vertical silicon fins extending above substrate 102, and are used to form source and drain regions (not shown) and channel regions therebetween. Shallow trench isolation (STI) regions 120 are formed to define fins 100. Gate 108 is formed over fins 100. Gate dielectric 106 is formed to separate fins 100 from gate 108.
In the formation of STI regions 120, a wet etch is used to recess the top surfaces of STI regions 120 to form fins 100. It is observed that with the wet etching, the center portions of the surfaces of STI regions 120 are lower than the portions of surfaces close to fins 100. The top surfaces of STI regions 120 are referred to as having a smiling profile.
It is realized that the parasitic capacitance (shown as capacitors 110) is generated between gate 108 and semiconductor strips 122, wherein STI regions 120 act as the insulator of parasitic capacitor 110. The parasitic capacitance adversely affects the performance of the respective integrated circuit, and needs to be reduced.